module top_module ( 
    input p1a, p1b, p1c, p1d,
    output p1y,
    input p2a, p2b, p2c, p2d,
    output p2y );

    wire	p1y0;
    wire	p2y0;
    
    and	and1	(p1y0, p1a, p1b, p1c, p1d);
    and	and2	(p2y0, p2a, p2b, p2c, p2d);
    not	not1	(p1y, p1y0);
    not	not2	(p2y, p2y0);

endmodule
